With each passing year, the importance of real time image processing is increasing due to rise in applications like remote sensing, advanced driver assistance systems and surveillance systems. Similarly, there is a rise in research involving hardware architecture that dehaze images with less area, speed, and power. In this paper, we propose a modification for a hardware architecture that does image dehazing in nine pipelined stages using saturation information to obtain local airlight and transmission of individual pixels to get the dehazed image. By adapting the idea of controlled logic behavior used in reversible logic gates which in turn is normally used in quantum computing and applying them in HDL, the proposed design modification maintains the same power dissipation of the original while reducing the logic element utilization compared to the original architecture. Furthermore, since our approach is pixel-based, it eliminates the need for an edge detection unit, which is typically required in patch-based methods. The proposed design operates at 12.958 MHz and utilizes 23% logic elements (LEs) when implemented on an FPGA platform.