Intelligent surveillance systems are becoming vital in ensuring security in smart cities, transportation centres, and critical infrastructure. However, these systems are challenged by the large amount of high-resolution video information, the high bandwidth demands of real-time processing, and the constrained computational resources at edge devices. Conventional embedded systems are not capable of providing the low latency and high throughput required to detect threats promptly and achieve the necessary accuracy when the system needs to be energy-efficient. To address these challenges, this paper proposes a novel low-latency and reconfigurable System-on-Chip (SoC) architecture that incorporates a multi-core neural accelerator specifically designed to execute various surveillance AI workloads, including object detection, behaviour analysis, and anomaly recognition. The SoC will feature dynamic reconfigurability of its hardware, enabling the adaptive sharing of computational units and bandwidth to manage changing workloads and multiple video streams effectively. This reconfigurability is also supported by an optimised dataflow pipeline that reduces the number of memory bottlenecks and speeds up inference, bringing real-time performance closer to reality. Additionally, in-chip pre-processing and feature extraction minimise the overhead of transmitting data to the destination, while also improving privacy by reducing the exposure of raw videos. Adaptive voltage-frequency scaling and selective core activation enhance power efficiency, making the design suitable for use in always-on edge deployments. Experimental results on standard surveillance data sets demonstrate that the proposed SoC can operate with sub-10-millisecond per-frame latency, support multiple high-definition stream video transactions, and achieve more than 85% inference accuracy at under 5 watts of power. This solution demonstrates significant gains in reducing latency, lowering energy consumption, and enhancing multi-camera processing compared to current AI accelerators and embedded platforms. The above findings validate the proposed reconfigurable SoC as a promising platform for next-generation intelligent surveillance systems that require rapid, accurate, and energy-efficient edge AI inference.

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Low-Latency Reconfigurable SoC with Multi-Core Neural Accelerators for Intelligent Surveillance

  • Hyba AbdulJaleel,
  • Hassan Mohamed Ali

摘要

Intelligent surveillance systems are becoming vital in ensuring security in smart cities, transportation centres, and critical infrastructure. However, these systems are challenged by the large amount of high-resolution video information, the high bandwidth demands of real-time processing, and the constrained computational resources at edge devices. Conventional embedded systems are not capable of providing the low latency and high throughput required to detect threats promptly and achieve the necessary accuracy when the system needs to be energy-efficient. To address these challenges, this paper proposes a novel low-latency and reconfigurable System-on-Chip (SoC) architecture that incorporates a multi-core neural accelerator specifically designed to execute various surveillance AI workloads, including object detection, behaviour analysis, and anomaly recognition. The SoC will feature dynamic reconfigurability of its hardware, enabling the adaptive sharing of computational units and bandwidth to manage changing workloads and multiple video streams effectively. This reconfigurability is also supported by an optimised dataflow pipeline that reduces the number of memory bottlenecks and speeds up inference, bringing real-time performance closer to reality. Additionally, in-chip pre-processing and feature extraction minimise the overhead of transmitting data to the destination, while also improving privacy by reducing the exposure of raw videos. Adaptive voltage-frequency scaling and selective core activation enhance power efficiency, making the design suitable for use in always-on edge deployments. Experimental results on standard surveillance data sets demonstrate that the proposed SoC can operate with sub-10-millisecond per-frame latency, support multiple high-definition stream video transactions, and achieve more than 85% inference accuracy at under 5 watts of power. This solution demonstrates significant gains in reducing latency, lowering energy consumption, and enhancing multi-camera processing compared to current AI accelerators and embedded platforms. The above findings validate the proposed reconfigurable SoC as a promising platform for next-generation intelligent surveillance systems that require rapid, accurate, and energy-efficient edge AI inference.