Scholarlink

This work presents a Total Memory Encryption and Authentication (TMEA) cache, implemented on a RISC-V processor, designed to protect against memory subsystem attacks. The industry-standard AES-GCM authenticated encryption algorithm, the proposed TMEA cache, transparently secures the confidentiality and integrity of every cache line. As a result, the evaluation shows that this robust security solution has minimal performance impact, introducing less than 4% overhead.

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Low-Overhead Total Memory Encryption and Authentication on a RISC-V Processor

  • 会议论文

  • 发表日期：

    2026年

查看全文
  • The-Binh Nguyen,
  • Cuong Pham-Quoc,
  • Tuan-Kiet Dang,
  • Cong-Kha Pham

摘要

This work presents a Total Memory Encryption and Authentication (TMEA) cache, implemented on a RISC-V processor, designed to protect against memory subsystem attacks. The industry-standard AES-GCM authenticated encryption algorithm, the proposed TMEA cache, transparently secures the confidentiality and integrity of every cache line. As a result, the evaluation shows that this robust security solution has minimal performance impact, introducing less than 4% overhead.