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This work presents the design, hardware implementation, and empirical evaluation of a secure and lightweight Federated Learning (FL) node architecture on Field-Programmable Gate Arrays (FPGAs). The proposed framework integrates a high-throughput Convolutional Neural Network (CNN) accelerator for on-device inference with a suite of dedicated hardware-based cryptographic primitives, including Advanced Encryption Standard (AES-128) for confidentiality, Secure Hash Algorithm (SHA-256) for integrity verification, Rivest–Shamir–Adleman (RSA) for digital signatures, and a True Random Number Generator (TRNG) using ring oscillator entropy sources. The architecture supports low-latency real-time inference and secure transmission of model updates, ensuring both data confidentiality and source authenticity. An optimized Universal Asynchronous Receiver-Transmitter Interface (UART) is used for efficient communication. The entire system is fully synthesized and has been prototyped on a Xilinx Zynq UltraScale platform, achieving high resource efficiency, cryptographic robustness, and operational suitability for deployment in privacy-sensitive AIoT environments.

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FPGA-Based Secure Federated Learning with CNN Inference and Hardware Cryptography

  • 会议论文

  • 发表日期：

    2026年

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  • Phuc Tran-Vinh,
  • Cuong Pham-Quoc

摘要

This work presents the design, hardware implementation, and empirical evaluation of a secure and lightweight Federated Learning (FL) node architecture on Field-Programmable Gate Arrays (FPGAs). The proposed framework integrates a high-throughput Convolutional Neural Network (CNN) accelerator for on-device inference with a suite of dedicated hardware-based cryptographic primitives, including Advanced Encryption Standard (AES-128) for confidentiality, Secure Hash Algorithm (SHA-256) for integrity verification, Rivest–Shamir–Adleman (RSA) for digital signatures, and a True Random Number Generator (TRNG) using ring oscillator entropy sources. The architecture supports low-latency real-time inference and secure transmission of model updates, ensuring both data confidentiality and source authenticity. An optimized Universal Asynchronous Receiver-Transmitter Interface (UART) is used for efficient communication. The entire system is fully synthesized and has been prototyped on a Xilinx Zynq UltraScale platform, achieving high resource efficiency, cryptographic robustness, and operational suitability for deployment in privacy-sensitive AIoT environments.