Enhanced Reliability Architecture for VLSI Systems Using the IRMC Algorithm for Error Detection and Correction
摘要
The problem of ensuring the integrity of data transmitted on the Internet in the context of modern mobile communication in an environment of increasing complexity transmissions is acute. To ensure protection against degradation due to channel noise and environmental interference, reliable error detection and correction must be used, especially at the data link layer. Communication networks are usually realized through two independent logical channels: a signaling and control channel and a data traffic channel. In the traffic channel, bits of information are then supplemented by an encoded correction code to create a powerful composite data stream that increases fault resilience during transmission. Current SRAM-based memory systems are fault-tolerant to a limited degree, but they are still vulnerable to Single Cell Upsets (SCUs) and Multiple Cell Upsets (MCUs); these are frequent events caused by exposure to high-energy particles, e.g., cosmic radiation. In order to overcome such vulnerabilities, this paper proposes an Improved Redundant Matrix Code (IRMC) method, which is particularly aimed at countering the effects of memory corruption by powerful detection and correction of various bit faults. Compared to traditional rescue codes, IRMC is highly superior in that it achieves a better detection rate, better correction ability, and reduced overheads in terms of space, power, and delay. Xilinx ISE 14.7 is used to realize the proposed solution, where the behavioral and structural modeling was done in Verilog HDL. Simulation and synthesis confirm IRMC improvement with regard to both error correction strength and hardware efficiency, and signal that it is a promising low-power, high-reliability coding scheme for next-generation memory protection.