Scholarlink

Ultra‑low‑power IoT nodes increasingly rely on tight co‑design of microelectromechanical systems (MEMS) and CMOS interface circuits to meet aggressive energy, noise, and form‑factor targets under cost constraints. This chapter presents a practical co‑design methodology that couples multiphysics MEMS modelling with low‑voltage, low‑noise readout, and power‑management circuits. We review integration options (monolithic, MEMS‑last, and heterogeneous wafer‑level bonding) and discuss implications for parasitics, thermal budget, packaging, and reliability. Design recipes are given for capacitive, resonant, and thermal/flow sensing, covering chopper‑stabilized charge/CTIA front‑ends, time/phase‑domain techniques with TDCs, and ADC/CDC choices tailored to duty‑cycled operation. We propose reporting checklists and comparable figures‑of‑merit and illustrate the methodology through recent case studies.

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

MEMS–CMOS Co‑design for Ultra‑Low‑Power IoT

  • 章节

  • 发表日期：

    2026年

查看全文
  • K. B. Sowmya,
  • K. Veena Divya

摘要

Ultra‑low‑power IoT nodes increasingly rely on tight co‑design of microelectromechanical systems (MEMS) and CMOS interface circuits to meet aggressive energy, noise, and form‑factor targets under cost constraints. This chapter presents a practical co‑design methodology that couples multiphysics MEMS modelling with low‑voltage, low‑noise readout, and power‑management circuits. We review integration options (monolithic, MEMS‑last, and heterogeneous wafer‑level bonding) and discuss implications for parasitics, thermal budget, packaging, and reliability. Design recipes are given for capacitive, resonant, and thermal/flow sensing, covering chopper‑stabilized charge/CTIA front‑ends, time/phase‑domain techniques with TDCs, and ADC/CDC choices tailored to duty‑cycled operation. We propose reporting checklists and comparable figures‑of‑merit and illustrate the methodology through recent case studies.