Junctionless architecture is the simplest architecture introduced so far which not only eases the manufacturing process but also provides excellent short channel effects. These attributes makes it a viable choice for deep nanoscale domain. Two design requirement of junctionless device are (1) heavy doping concentration (~ 1018–1019 cm−3) in all the three regions viz. source, drain, and channel, and (2) high gate work function (~ 5.0 eV). These design constraint leads to the two major challenges in junctionless-based device—low ON-state current and high device-to-device variations. To address these challenges, Strained Engineered Multi-fin Lightly Doped Junctionless FinFET (Strained Multi-fin LD JL-FinFET) structure is proposed in this work. To design this structure, strained silicon directly-on-insulator (SSOI) technique is used. The use of low doping concentration solves two important issues of JL-FinFET. It reduces the device variability and also relaxes the high gate work function requirement of JL devices. Furthermore, replacing silicon with strained film in the channel region along with multi-fin structure brings out the improvement in the ON-state current. This work presents the analysis and comparison of 14 nm conventional heavily doped JL-FinFET (HD JL-FinFET) with proposed strained multi-fin LD JL-FinFET. The simulated results shows proposed design exhibits better short channel behavior in terms of ON/OFF-current ratio, SS, DIBL, etc., along with high ON-state current.