Design and FPGA Implementation of Reversible Logic-Based Multiplier for Efficient Cryptographic Operations

The need for efficient and low-power hardware accelerators for cryptographic algorithms has led to significant advancements in digital design. This paper presents the design and FPGA implementation of a reversible logic gates-based multiplier optimized for cryptographic operations. Utilizing Peres and HNG gates, the design aims to minimize quantum cost, gate count, garbage output, and TRLIC, enhancing overall system performance and energy efficiency. The proposed multiplier is evaluated against existing designs, focusing on metrics such as quantum cost, garbage output, ancilla input, Total Reversible Logic Instruction Count (TRLIC), number of gates used, and delay. The FPGA implementation demonstrates the practicality and effectiveness of the design, showcasing its potential for real-world applications. The findings provide valuable insights into the trade-offs and benefits of using reversible multipliers, contributing to the development of future-proof hardware solutions in the realm of cryptographic operations. A multiplier circuit that is optimized has been designed and developed using HNG and PERES gates. Using Xilinx Vivado and Xilinx Ise 14.7, the simulations are performed. The NEXYS A7 (Artix 7 series) board has been used for FPGA implementation. Ultimately, it’s mentioned that as in addition to improving the delay, there is a significant 50.36% reduction in the quantum cost.