Post-quantum cryptographic algorithms can resist attacks from quantum computers and address the threat posed by quantum computing to public key cryptography. However, post-quantum key exchange and digital signature protocols consume a significant amount of memory, making it difficult to directly deploy them on embedded IoT devices with limited computing resources and memory space. To address the deployment challenges and limited practicality of post-quantum cryptographic algorithms on embedded devices, we propose an optimized implementation scheme for lattice-based post-quantum cryptographic algorithm NTRU on the RISC-V platform. The aim is to achieve constant-time polynomial convolution operations for NTRU on embedded devices. Firstly, designing computation flows suitable for convolution operations in NTRU. Secondly, proposing a constant-time address correction algorithm and hybrid multiplication techniques to enhance the efficiency of NTRU convolution operations on the RISC-V platform. Finally, based on the concept of product-form polynomials, the generation and computation methods for sparse polynomials are redesigned to support convolution operations using product-form polynomials, thereby reducing the time complexity of polynomial multiplication in NTRU. By comparing clock cycles, this paper’s approach demonstrates a 60% performance improvement over the modular multiplication operation proposed by Guillen et al. on the 32-bit Cortex-M0 platform. Performance optimization is achieved at both the 128-bit and 256-bit security levels, indicating good practicality.