Binary adders are one of the most important basic units used in arithmetic operations. Several types of adders have been proposed in literature for various applications. Some authors have modified the basic adder architectures and some have proposed an altogether new architectures for the addition process. In all these architectures, the bottleneck problem has always been the carry propagation path, which is the critical path also. So, all the efforts put by various authors have been in optimizing the carry path in order to enhance the performance of the binary adders. In this paper, we propose a new adder architecture for performing binary addition operation. The architecture is based on a proposed novel half-adder circuit. There is an improvement of around 18% in terms of delay.