An Adiabatic adder is designed using the Efficient Charge Recovery Logic (ECRL) technique. This study compares adiabatic adders with the FinFET logic-based adder. Both the adders are implemented, designed, and analyzed with 180 nm FinFET technology. The time delay, power dissipation, and power delay product (PDP) of both the adders are calculated, and all values analyzed at a voltage range from 0 to 1 V at a frequency of 200 MHz. Based on the results obtained, the adiabatic adders can perform better than FinFET adders in terms of power dissipation. The number of transistors required to design an ECRL adder is comparatively less than the FinFET adder. The power dissipation of ECRL adders is 73% less than the FinFET adders. This technology is mainly used in the fabrication of circuits under nanotechnology.