Physical design (PD) is a critical step in VLSI chip design. PD is placing design block in netlist in a layout which will mimic silicon placement. PD consists of many steps to convert a netlist to a physical layout. As more and more logic is packed in smaller technology nodes, it has become critical to optimize every step in PD flow. This chapter elaborates on various methods that can be used for optimizing PD flow. It discusses many algorithms which help with PD flow. Heterogenous FPGAs—PhetDP are key algorithms used to optimize whole flow. Algorithms like Genetic algorithms-based approach to solve Clustered Steiner tree problem are applicable here. Accelerating algorithms such as accelerated computation of Steiner trees on GPUs, Goal oriented shortest path search and Fast DSE of reconfigurable accelerator systems are also elaborated in this chapter. Thermal hotspots are aware of multi-level routing and heuristic search for MEC, optimized placement solution for mixed size designs and circuit partitioning algorithms, partition models and algorithm parallelization are also discussed in this chapter. Authors have surveyed and discussed all these algorithms in detail.