Spiking Neural Networks (SNNs) represent a cutting-edge advancement in neural network architecture. Unlike traditional neural networks that depend on continuous input processing, spiking neural networks (SNNs) utilize discontinuous spikes to facilitate event-driven computation. In this paper, we propose an SNN circuit for handwritten digit recognition using 180 nm CMOS technology in Cadence Virtuoso. The proposed architecture consists of four fundamental circuits: neurons, synapses, spike-timing-dependent plasticity (STDP), and a winner-take-all (WTA) mechanism. Although inspired by convolutional neural networks (CNNs), our design features a more compact four-layer structure consisting of an output layer, two hidden layers, and an input layer. Experimental validation demonstrates the feasibility of the proposed approach for low power-constrained digit classification. However, reduced network depth limits classification accuracy, particularly in distinguishing overlapping patterns. These findings highlight the trade-off between hardware efficiency and recognition performance, providing insight for future optimizations in neuromorphic circuit design.