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To study the feasibility of a shallow-depth neutrino detector, a Cosmic Muon Veto Detector (CMVD) is being built at TIFR, Mumbai. The CMVD will consist of extruded plastic scintillators and SiPMs, requiring an efficiency of \(99.99\%\) and a false count rate of \(10^{-5}\) or lower. To achieve this, a high-speed, low-noise DAQ system is necessary. SiPM signals are used for charge measurement, while triggers come from RPC detectors. Due to latency, a temporary storage system is needed to preserve the signal for acquisition. The DRS4 chip, from PSI, Switzerland, is suitable for this purpose, operating at \(1\,GSa/s\) with a \(1\,V_{pk-pk}\) input range. With typical SiPM pulse characteristics, a \(1\,ns\) sampling time is sufficient. Proper offset correction, a suitable ADC, and fast electronics are essential to achieve full dynamic range and resolution for muon pulses.

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Suitability of DRS4 for Readout of SiPMs in the CMVD

  • 会议论文

  • 发表日期：

    2025年

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  • Prajjalak Chattopadhyay,
  • Mandar N. Saraf,
  • Gobinda Majumder,
  • Satyanarayana Bheesette,
  • Suresh S. Upadhya

摘要

To study the feasibility of a shallow-depth neutrino detector, a Cosmic Muon Veto Detector (CMVD) is being built at TIFR, Mumbai. The CMVD will consist of extruded plastic scintillators and SiPMs, requiring an efficiency of \(99.99\%\) and a false count rate of \(10^{-5}\) or lower. To achieve this, a high-speed, low-noise DAQ system is necessary. SiPM signals are used for charge measurement, while triggers come from RPC detectors. Due to latency, a temporary storage system is needed to preserve the signal for acquisition. The DRS4 chip, from PSI, Switzerland, is suitable for this purpose, operating at \(1\,GSa/s\) with a \(1\,V_{pk-pk}\) input range. With typical SiPM pulse characteristics, a \(1\,ns\) sampling time is sufficient. Proper offset correction, a suitable ADC, and fast electronics are essential to achieve full dynamic range and resolution for muon pulses.