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A cosmic muon veto detector (CMVD) is being built around the RPC detector at TIFR, Mumbai, to explore the feasibility of a shallow-depth neutrino detector. It uses extruded plastic scintillator (EPS) strips with SiPMs for muon detection, requiring over 99.99% efficiency. A DRS4-based readout system samples the SiPM signals at 1 GSa/s, with data acquisition managed by an AMD Spartan-7 FPGA and a microblaze softcore processor. The paper discusses the prototype design of the SiPM readout board using the DRS4 ASIC and the FPGA.

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Design and Development of DRS4 and FPGA Based DAQ Board for the CMVD

  • 会议论文

  • 发表日期：

    2025年

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  • Mandar Saraf,
  • Satyanarayana Bheesette,
  • Prajjalak Chattopadhyay,
  • Yuvaraj Elangovan,
  • Ravindran K C,
  • Gobinda Majumder,
  • Ravindra Shinde,
  • Suresh Upadhya

摘要

A cosmic muon veto detector (CMVD) is being built around the RPC detector at TIFR, Mumbai, to explore the feasibility of a shallow-depth neutrino detector. It uses extruded plastic scintillator (EPS) strips with SiPMs for muon detection, requiring over 99.99% efficiency. A DRS4-based readout system samples the SiPM signals at 1 GSa/s, with data acquisition managed by an AMD Spartan-7 FPGA and a microblaze softcore processor. The paper discusses the prototype design of the SiPM readout board using the DRS4 ASIC and the FPGA.