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This paper presents a hybrid architecture neural network accelerator based on FPGA and ASIC. The proposed accelerator is employed to expedite the inference process for CNN and MHA modules, accommodating data of varying accuracy. Its application extends to image-to-sequence models. The paper also puts forward a controller with an appropriate instruction set to drive the data flow, and discusses how to configure the accelerator in coordination with a particular model. The efficacy of the proposed accelerator is demonstrated through experimental evaluations, which yield acceleration ratios of at least 3.0x for a single layer and approximately 1.5x for an entire network.

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Hybrid Architecture Accelerator Co-design for DNN on FPGA and ASIC

  • 会议论文

  • 发表日期：

    2026年

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  • Honghao Zhang,
  • Ruidong Li,
  • Ji Zhong,
  • Meizhou Gao,
  • Xinyi Le

摘要

This paper presents a hybrid architecture neural network accelerator based on FPGA and ASIC. The proposed accelerator is employed to expedite the inference process for CNN and MHA modules, accommodating data of varying accuracy. Its application extends to image-to-sequence models. The paper also puts forward a controller with an appropriate instruction set to drive the data flow, and discusses how to configure the accelerator in coordination with a particular model. The efficacy of the proposed accelerator is demonstrated through experimental evaluations, which yield acceleration ratios of at least 3.0x for a single layer and approximately 1.5x for an entire network.