As computational workloads continue to scale exponentially, modern spatial accelerators have emerged as critical enablers due to their superior parallelism, architectural flexibility, and scalable design. However, the increasing die size introduces significant hardware defect challenges that degrade both computational performance and manufacturing yield. While spatial architectures typically incorporate redundant resources for defect tolerance, effectively leveraging these redundancies presents substantial optimization challenges. This paper proposes a hierarchical defect recovery methodology that strategically balances repair efficiency with architectural scalability. Our dual-phase approach synergistically combines intra-chiplet task remapping for optimized local redundancy repairing with inter-chiplet rescheduling that enables global load balancing when local redundancy is exhausted. We formulate this dual-phase optimization problem and develop a comprehensive framework that navigates critical tradeoffs between defect avoidance, spatial locality preservation, and network-on-chip efficiency. Experimental evaluations across diverse defect scenarios demonstrate 35.17% to 50.11% performance improvements over baseline methods, while maintaining over 80% of ideal performance even in severe defect conditions.