A 14 T Low-Power High-Speed Full Adder Circuit

This chapter presents the design and simulation of a 14 T low-power, high-speed full adder (FA) circuit. The performance of the proposed FA was evaluated and compared to other existing full adder designs. A comprehensive set of key performance indicators, such as propagation delay, power consumption, energy-delay product (EDP), and power-delay product (PDP), were considered for the analysis. The simulation results show that the 14 T FA outperforms the other designs across all evaluated metrics. Through the optimization of transistor sizing, the proposed 14 T FA achieves the lowest values for power consumption, PDP, and EDP among the designs considered. Specifically, the 14 T FA consumes an average power of 2.25 μW and exhibits a PDP of 32.49 aJ when operating at a frequency of 200 MHz. These results underscore the potential of the 14 T FA design as an efficient solution for low-power, high-performance digital circuit applications.