Scholarlink

With a focus on increased write margin, a unique 7T SRAM architecture has been put forth in this study. In addition to standard VTH devices at the 32nm CMOS technology node, the design includes a low-threshold voltage (VTH) MOS as a feedback path between the inverter pairs. In contrast with previous SRAM architectures, the cell presented exhibits a noticeable betterment in write margin, SNM, power consumed and delay. The cell presented has read-1 (read-0) power of 887.2 nW (10.09 µW) and a write-1 (write-0) power of 1087 nW (26.6 µW). 8T, 9T, and 10T cells had write-1 powers of 112.2%, 113.70%, and 136.11% of power of the novel SRAM cell presented.

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Stability Analysis of Robust 7T SRAM Cell for 32 nm CMOS

  • 会议论文

  • 发表日期：

    2026年

查看全文
  • Arunima Tripathi,
  • Poornima Mittal

摘要

With a focus on increased write margin, a unique 7T SRAM architecture has been put forth in this study. In addition to standard VTH devices at the 32nm CMOS technology node, the design includes a low-threshold voltage (VTH) MOS as a feedback path between the inverter pairs. In contrast with previous SRAM architectures, the cell presented exhibits a noticeable betterment in write margin, SNM, power consumed and delay. The cell presented has read-1 (read-0) power of 887.2 nW (10.09 µW) and a write-1 (write-0) power of 1087 nW (26.6 µW). 8T, 9T, and 10T cells had write-1 powers of 112.2%, 113.70%, and 136.11% of power of the novel SRAM cell presented.