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SAR ADCs have emerged as popular solutions for applications requiring high accuracy, moderate speed, compactness, and cost-effectiveness. Extensive research has been dedicated to enhancing the precision of commercial successive approximation SAR ADCs, owing to their crucial role in delivering accurate analog-to-digital conversions. However, achieving this precision necessitates precise internal digital-to-analog converter (DAC) circuitry, typically implemented using capacitors (C-DAC) to optimize power consumption. In this article, our focus is on implementing a capacitive DAC for a 16-bit SAR ADC using Verilog. Through comprehensive simulation and verification processes, we evaluate the functionality, performance, and reliability of the designed C-DAC, considering factors such as power consumption, area utilization, and conversion accuracy. Ultimately, this article contributes to advancing the field of SAR ADC design by providing a practical implementation of a key component essential for achieving superior analog-to-digital conversion performance.

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Design and Simulation of a High-Speed 16-Bit Successive Approximation Register ADC (SAR ADC) with Capacitive-DAC Implementation Using Verilog

  • 会议论文

  • 发表日期：

    2026年

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  • M. Keerthana,
  • K. Ragini,
  • D. Anjali,
  • M. Harshitha,
  • S. Akshitha

摘要

SAR ADCs have emerged as popular solutions for applications requiring high accuracy, moderate speed, compactness, and cost-effectiveness. Extensive research has been dedicated to enhancing the precision of commercial successive approximation SAR ADCs, owing to their crucial role in delivering accurate analog-to-digital conversions. However, achieving this precision necessitates precise internal digital-to-analog converter (DAC) circuitry, typically implemented using capacitors (C-DAC) to optimize power consumption. In this article, our focus is on implementing a capacitive DAC for a 16-bit SAR ADC using Verilog. Through comprehensive simulation and verification processes, we evaluate the functionality, performance, and reliability of the designed C-DAC, considering factors such as power consumption, area utilization, and conversion accuracy. Ultimately, this article contributes to advancing the field of SAR ADC design by providing a practical implementation of a key component essential for achieving superior analog-to-digital conversion performance.