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A multiplier is an essential part of many digital integrated circuits (ICs) used in arithmetic computations. Multipliers for modern VLSI (Very Large-Scale Integration) circuits must be quick, power-efficient, and small in size. In the quickly changing world of today and in the current technological environment, the widespread use of computers and the Internet has been facilitated by the need for strong and quick data processing. Nevertheless, using parallel computing effectively satisfies these expectations. In particular, it offers a brand-new method for utilizing Systolic Architecture on Field Programmable Gate Arrays (FPGAs) and other Reconfigurable Systems (RS) to speed up Matrix Multiplication. Systolic arrays are highly parallel computer architectures that can handle difficulties by performing operations on data pieces in parallel. This makes them ideal for jobs like matrix multiplication. Our main goal is to create a system that greatly increases data processing speed while minimizing path delay. We can accomplish this by using Xilinx Software. Because FPGAs may be used to customize and reconfigure hardware, they are a great option for optimizing systolic array topologies to meet certain computing requirements. An effective way to process data at high speeds in complicated computational settings is to leverage the capabilities of parallel computing on FPGA devices.

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A Power Efficient Systolic Array Architecture-Based Multiplier for DSP Applications

  • 会议论文

  • 发表日期：

    2026年

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  • Bhattu Hari Prasad Nayak,
  • Sravan K. Vittapu,
  • Gangadi Chandra Vardhan Reddy,
  • Dindu Akhil goud,
  • Banuka Sanjay

摘要

A multiplier is an essential part of many digital integrated circuits (ICs) used in arithmetic computations. Multipliers for modern VLSI (Very Large-Scale Integration) circuits must be quick, power-efficient, and small in size. In the quickly changing world of today and in the current technological environment, the widespread use of computers and the Internet has been facilitated by the need for strong and quick data processing. Nevertheless, using parallel computing effectively satisfies these expectations. In particular, it offers a brand-new method for utilizing Systolic Architecture on Field Programmable Gate Arrays (FPGAs) and other Reconfigurable Systems (RS) to speed up Matrix Multiplication. Systolic arrays are highly parallel computer architectures that can handle difficulties by performing operations on data pieces in parallel. This makes them ideal for jobs like matrix multiplication. Our main goal is to create a system that greatly increases data processing speed while minimizing path delay. We can accomplish this by using Xilinx Software. Because FPGAs may be used to customize and reconfigure hardware, they are a great option for optimizing systolic array topologies to meet certain computing requirements. An effective way to process data at high speeds in complicated computational settings is to leverage the capabilities of parallel computing on FPGA devices.