When comparing various processor types, it is found that RISC-based processors work better for applications requiring faster processing times and lower power consumption than CISC-based CPUs. This paper focuses on the design and implementation of a low-power 32-bit RISC-V processor, targeting improved power efficiency for battery-operated devices. For RISC- V processors, area optimization and power optimization are two significant factors that influence performance. Some of the most important power optimization techniques available for RISC-V processors are clock gating, dynamic voltage and frequency scaling (DVFS), pipeline stage optimization, instruction-level parallelism (ILP), cache optimization, dynamic power management (DPM), and power gating. Among these power-saving methods, clock gating stands out as a fundamental approach for reducing power consumption in RISC-V processors. As the central processing unit of processor, the arithmetic logical unit (ALU) requires effective strategies to achieve minimal power consumption. Therefore, introducing major clock gating techniques, flip-flop-based gating, latch-based gating, and adding a dedicated gating unit to the ALU leads to major power savings for RISC-V processors. The RISC-V processor design was developed in Verilog HDL and implemented on an Artix-7 FPGA, and gate-level synthesis using the SCL 180nm technology library in Cadence Genus. In both implementation cases, the 32-bit RISC-V processor with flip-flop gated ALU consumed 15 \(\%\) less power compared to other gating techniques. Layout, placement, and routing were performed using Cadence Innovus, resulting in optimized post-routing metrics, including a power consumption of 0.185962 nW and an area of 54362.56 \(\upmu \text {m}^{2}\) .