Timer functionality in System-on-Chip (SoC) designs is pivotal, particularly in implementations where timers are instrumental in task scheduling, time management, and precise system synchronization. Among these timers, the Advanced Peripheral Bus (APB) timer plays a crucial role in orchestrating time-sensitive operations, precise system synchronization, and coordinating essential tasks within the SoC, thereby contributing significantly to its overall reliability. Given the critical role of timers in SoC operation, thorough verification is essential to ensure that these timers operate accurately and reliably within the system, preventing potential timing errors and ensuring the overall functionality and performance of the SoC. The main focus of this work is the design and implementation of a 32- bit APB timer and its verification using Universal Verification Methodology (UVM). The 32-bit architecture of timer offers high resolution and precision, making it suitable for a wide range of timing-critical tasks. UVM is the most reliable method to verify a 32-bit APB timer as it integrates with SystemVerilog to provide a modular, reusable, and scalable verification environment. So, in this work we focus on build a comprehensive UVM environment using SystemVerilog to rigorously test the timer’s functionality, including its ability to decrement from a preset value to zero and generate an interrupt. The proposed environment UVM has testbench with its sequencer, driver, monitor, and coverage collectors. This ensures comprehensive validation of the timer’s operations with compliance with APB protocol. Simulations were conducted using Synopsys DVE, achieving an overall coverage of 96.08%. Coverage analysis was performed with Synopsys Verdi, confirming the robustness and reliability of the timer design.