Traditional chip verification methods, especially coverage-directed random testing, face inefficiencies due to the increasing complexity of modern integrated circuits. We propose HALOES, a machine learning framework optimizing stimuli intelligently to boost test efficiency. It integrates a graph probability model with Bayesian inference to analyze instruction flows and extract features, then uses clustering to prioritize test cases.​ HALOES outperforms conventional random testing, achieving similar coverage in less time on multiple benchmarks. Its effectiveness comes from adaptive learning and redundancy reduction via cluster-based filtering. Innovations include using Bayesian networks for acquisition of embedding representations and a KMeans clustering approach to balance coverage and eliminate unproductive stimuli.​ Industry-standard testbench experiments confirm HALOES accelerates coverage closure while ensuring verification quality. This data-driven approach offers a scalable solution for post-silicon validation, especially for complex SoC designs.