Challenge for FD-ISAC

This chapter, based on previous discussions, provides an in-depth analysis of the main challenges and development trends of FD-ISAC technology within current research. In terms of model design, the discussion addresses deficiencies in performance metrics, performance boundaries, precise modeling of self-interference, joint waveform design, and integrated channel models. For signal processing, this chapter also explores issues regarding echo signal recognition, the trade-off between algorithm accuracy and complexity, and resource allocation. Concerning FD-ISAC implementation and chip integration, this chapter highlights current challenges such as frequency and bandwidth limitations, as well as complexity and power consumption issues in the chip process. Research on FD-ISAC systems is still in its early stages. Although many concepts have been proposed and analyzed through simulations, and some preliminary experiments have been conducted, experimental research remains basic. Current studies face several challenges: model design, signal processing, realization and on-chip implementation.