On-Chip RF Canceller

With the increasing demands of wireless communications, higher requirements of miniaturization and integration have been put forward for communication devices. Compared with the discrete-component-based implementations, on-chip RF cancellers would permit the design of commercially attractive compact FD ISAC devices [1], which is recognized as a key technology for large-scale applications by academia and industry. Accordingly, this chapter presents on-chip monolithic designs for RF SIC, including frequency-domain equalization (FDE) SIC architecture, time-domain equalization (TDE) SIC architecture, Hilbert-transform equalization (HTE) SICSelf-Interference Cancellation architecture and MIMO SIC architecture, as depicted in Fig. 6.1. A detailed investigation is provided into key technologies, cancellation performance, as well as the advantages and disadvantages of each of these four architectures.