Hardware Implementation of FD-ISAC

Recently, several hardware platforms have been proposed to validate the feasibility of FD-ISAC systems. In the following subsections, we will provide a comprehensive investigation of these hardware implementations. Specifically, we will delve into the hardware realizations of FD SIC techniques, which are crucial for mitigating SI in simultaneous transmission and reception scenarios. FD SIC techniques can be categorized into three domains: antenna-domain, RF-domain and digital-domain, and their respective hardware implementations are described. Moreover, the FD testbeds that integrate these three-domain SIC techniques are also investigated, which can achieve more than 120 dB cancellation performance over 20 MHz bandwidth. Additionally, we will explore the hardware platforms designed for FD sensing, focusing on their ability to simultaneously perform sensing and communication tasks in an efficient and integrated way. Through this investigation, we aim to highlight the latest advancements in the development of hardware solutions for FD-ISAC. However, it should be noted that hardware implementations of FD-ISAC remain in the early stages.