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Timing closure during the Engineering Change Order (ECO) stage, remains a major challenge in advanced integrated circuit design as circuit complexity increases. Although pre-placed spare cells support post-layout fixes, many spare-cell ECO methods emphasize allocation policies rather than maximizing timing recovery using accurate net-delay impact. This paper presents an automated timing-driven spare-buffer rewiring ECO framework that tightly couples the static timing analysis stage with the physical design stage to perform localized, delay-optimized timing repair. The framework identifies the worst-slack nets along the data path, constructs path-specific bounding boxes to constrain candidate spare buffers, estimates source-to-spare and spare-to-sink delays using Manhattan-distance-based wire-delay models and applies a spare-locking mechanism to ensure conflict-free reuse across iterations. The approach is evaluated in 32 nm technology on five benchmark instances spanning a 4 by 4 DCT core, an FP64 unit, and a pipelined MAC design. Overall, spare-buffer rewiring reduces ECO-critical path violations substantially more than conventional gate sizing, achieving an average ECO-path resolution of about 73% across all benchmark instances, compared with about 59% for gate sizing. Consistent with these results, the proposed method delivers higher TNS gain defined as pre-ECO TNS minus post ECO TNS and reduces runtime by up to about 26% versus gate sizing, while maintaining low overhead with total cell area increase below 0.15% and power overhead below 4%.

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Spare-Buffer Cell Rewiring for Efficient Timing Engineering Change Order

  • 会议论文

  • 发表日期：

    2026年

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  • Nik Muhammad Afif Nik Rumzi,
  • Mohd Shahrizal Rusli,
  • Ab Al-Hadi Ab Rahman,
  • Muhammad Nadzir Marsono,
  • Haslina Md. Sarkan,
  • Fakhrul Zaman Rokhani

摘要

Timing closure during the Engineering Change Order (ECO) stage, remains a major challenge in advanced integrated circuit design as circuit complexity increases. Although pre-placed spare cells support post-layout fixes, many spare-cell ECO methods emphasize allocation policies rather than maximizing timing recovery using accurate net-delay impact. This paper presents an automated timing-driven spare-buffer rewiring ECO framework that tightly couples the static timing analysis stage with the physical design stage to perform localized, delay-optimized timing repair. The framework identifies the worst-slack nets along the data path, constructs path-specific bounding boxes to constrain candidate spare buffers, estimates source-to-spare and spare-to-sink delays using Manhattan-distance-based wire-delay models and applies a spare-locking mechanism to ensure conflict-free reuse across iterations. The approach is evaluated in 32 nm technology on five benchmark instances spanning a 4 by 4 DCT core, an FP64 unit, and a pipelined MAC design. Overall, spare-buffer rewiring reduces ECO-critical path violations substantially more than conventional gate sizing, achieving an average ECO-path resolution of about 73% across all benchmark instances, compared with about 59% for gate sizing. Consistent with these results, the proposed method delivers higher TNS gain defined as pre-ECO TNS minus post ECO TNS and reduces runtime by up to about 26% versus gate sizing, while maintaining low overhead with total cell area increase below 0.15% and power overhead below 4%.