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The paper presents supervised regression techniques to analyze subthreshold leakage current in MOSFETs. It integrates synthetic measurement data with both linear and nonlinear modeling approaches. The dataset generated from practical device parameters. It is injected by gaussian noise and offset bias. It simulates real-world measurement variability. Linear regression on the logarithmic Isub-Vgs transformation provided Io = 5.019x10−9A and n = 2.75. It produces mean absolute percentage errors (MAPE) of 16.36% and 93.31%, respectively. Nonlinear curve fitting is treated as a parametric optimization problem. It achieved reduced n error (29.82%) and increased Io error (66.67%). It illustrates model bias-variance trade-offs. Subthreshold slope predictions exceed the 59.87 mV/dec. Feature-derived gate voltage efficiency improved from 0.667 V/V to 0.702 V/V. Increased off-state leakage (+61.9%) confirms the necessity of incorporating additional features into predictive models for low-power device analysis.

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Modeling Subthreshold Leakage in MOSFETs: Supervised Regression with Noise-Aware Synthetic Datasets

  • 会议论文

  • 发表日期：

    2026年

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  • Tripti R. Kulkarni,
  • Arun Vikas Singh,
  • R. Manjunatha Prasad,
  • Suma Santosh,
  • Nagaraj M. Lutimath,
  • P. B. Savitha,
  • G. Vasudeva

摘要

The paper presents supervised regression techniques to analyze subthreshold leakage current in MOSFETs. It integrates synthetic measurement data with both linear and nonlinear modeling approaches. The dataset generated from practical device parameters. It is injected by gaussian noise and offset bias. It simulates real-world measurement variability. Linear regression on the logarithmic Isub-Vgs transformation provided Io = 5.019x10−9A and n = 2.75. It produces mean absolute percentage errors (MAPE) of 16.36% and 93.31%, respectively. Nonlinear curve fitting is treated as a parametric optimization problem. It achieved reduced n error (29.82%) and increased Io error (66.67%). It illustrates model bias-variance trade-offs. Subthreshold slope predictions exceed the 59.87 mV/dec. Feature-derived gate voltage efficiency improved from 0.667 V/V to 0.702 V/V. Increased off-state leakage (+61.9%) confirms the necessity of incorporating additional features into predictive models for low-power device analysis.