Sigma Delta DACs for Low Latency High Sampling Rate Audio on an FPGA
摘要
This paper presents a novel approach to ultra-low latency implementation of Sigma Delta (SD) Digital-to-Analog Converters (DACs) on Field Programmable Gate Arrays (FPGAs). We detail the design, simulations, and VHDL implementation of the proposed SD DACs. The paper provides an approach for a design-space exploration to find a tradeoff between the internal word lengths of calculations in the DAC and the Signal to Noise Ratio (SNR) of the output audio signal. In simulations, the proposed DAC can achieve an SNR of approximately 170 dB for input sample rates of 48 kHz - 768 kHz with the IP running at 49.152 MHz, resulting in an Oversampling Ratio (OSR) of 1024 - 64. In measurements, the DAC provides a latency inferior to 1 \(\upmu \) s. Our SD DAC implementation has been integrated as an IP core to the SyFaLa toolchain, which aims to facilitate the prototyping of real-time audio Digital Signal Processing (DSP) applications on FPGA.