Fault injection attacks exploit physical disturbances to compromise the functionality and security of integrated circuits. As System-on-Chip (SoC) architectures grow in complexity, the vulnerability of on-chip communication buses has become increasingly prominent. Buses, serving as interconnects among various IP cores, represent potential attack vectors for fault-based exploitation. In this study, we perform simulation-driven fault attack injection across three mainstream bus protocols— Wishbone, AXI-Lite, and AXI. We systematically examine fault attack success rates, spatial vulnerability distributions, and timing dependencies to characterize how faults interact with bus-level transactions. The results uncover consistent behavioral patterns across protocols, offering practical insights for both attack modeling and the development of resilient SoC designs.