This work presents the design and performance evaluation of a power-efficient dynamic latch-based comparator targeted for mixed-signal and energy-constrained applications. This work addresses the growing demand for ultra-low-power operation in portable and battery-operated electronic systems. The proposed architecture incorporates a clock-gated dynamic latch that is activated only during the evaluation phase, thereby effectively eliminating unnecessary switching activity and reducing static leakage power. The comparator is designed and simulated using a 0.18-µm CMOS process in the Cadence Virtuoso environment. Simulation results demonstrate a substantial power reduction of approximately 80.27%, with average power consumption reduced from 4.061 mW in the conventional design to 801.5 µW in the proposed architecture. Despite the significant power savings, the comparator preserves key performance metrics, including low propagation delay, fast switching speed, and robustness against process, voltage, and temperature (PVT) variations. These characteristics make the proposed design well suited for integration into SAR ADCs, biomedical sensing systems, and IoT-based sensor interfaces, where low power consumption and high accuracy are critical requirements.