As one of the core basic software tools in modern processor architecture, the compiler plays a key role in hardware resource utilization and program performance optimization. Addressing the dual challenges of limited register resources and low instruction-level parallelism efficiency faced by LDSP accelerator in the embedded real-time control domain, this paper conducts research on instruction scheduling optimization based on the LLVM compilation framework. Traditional heuristic scheduling methods, lacking dynamic register pressure sensing mechanism, frequently cause register spilling during the processing of large-scale data computations, resulting in a large number of redundant memory access instructions, which seriously restricts the release of hardware performance. To this end, this paper proposes an instruction scheduling algorithm based on quantification register pressure (QRP) and an improved Max-Min Ant System (MMAS). This algorithm estimates program performance by sensing the number of memory access instructions required for register spilling and guides instruction scheduling to achieve synergistic optimization of instruction-level parallelism and register pressure. Testing with eight classic DSP algorithms, the experimental results show that the algorithm can achieve an average performance speedup ratio of 1.1, effectively enhancing the performance of LDSP in computation-intensive programs.