This paper presents an optimized 16-bit Braun multiplier architecture that incorporates a custom-designed 15:4 compressor to improve performance. Conventional Braun multipliers, although structurally regular, face limitations in speed due to the ripple carry adder used for partial product accumulation. In this work, a 15:4 compressor composed of 5 full adders, two 5:3 compressors, and a 4-bit parallel adder is introduced in the reduction stage of the multiplier. The design is implemented in Verilog HDL and synthesized on a Xilinx Spartan-6 FPGA using the Xilinx ISE toolchain. Simulation and power analysis confirm that the proposed architecture significantly reduces propagation delay and offers a modest reduction in power consumption compared to the traditional Braun multiplier. These improvements make it suitable for high-performance digital signal processing and arithmetic-intensive VLSI applications.