As traditional Complementary Metal-Oxide-Semiconductor (CMOS) transistor technology nears its physical and economic scaling limits, like cost, complexity, and diminishing demand, the need for alternative nanoscale computing paradigms becomes increasingly critical. Quantum-dot Cellular Automata (QCA) has emerged as a leading candidate for next-generation nano-electronics, offering significant advantages in terms of high device density, fast switching capabilities, and ultra-low power consumption. This research work proposes a data handling circuit design for a 2 × 1 Multiplexer, a 1 × 2 Demultiplexer, and a 2 × 4 Decoder on a single layer with synchronized QCA clocking methodology utilizing 45-degree rotation cell in DEMUX and Decoder. The objective is to reduce overall layout complexity, eliminate the need for multi-layer interconnect structure design, and enhance performance metrics i.e. latency (delay), cell count, and area utilization. All proposed circuit layout designs are simulated by using the QCADesigner-E and the results are efferent against existing designs.