One of the most desired features of modern technology is the reduced power consumption of electronic equipment. Static random access memory (SRAM), a key piece of most electronic devices, suffers from static power dissipation due to leakage current. This is particularly significant for mobile devices with a brief power source. To minimize static power consumption, this work presents a 7T SRAM cell body bias controller adopted at the 45 nm CMOS technology node. Also, the proposed design has a lower threshold voltage, resulting in reduced write delay. When compared to a 6T SRAM cell and a 7T SRAM cell, respectively, the proposed model has been shown to yield 41%, 27% less static power dissipation. 40.8% and 29%. Therefore, the proposed design could be an excellent alternative for low-power SRAMs. Hence the proposed design will be implemented using enhanced power dissipation and reduction of delay using CMOS 45 nm nano technology technology.