This paper describes the development of an IP soft processor core based on the open and extensible RISC-V architecture implemented in Verilog. The design evolves from a multistage microarchitecture to a multithreaded core using shadow register sets, where each thread stores its architectural state and is dynamically mapped to general-purpose registers (x0–x31) and the program counter during execution. The multithreaded approach improves the efficiency of integrating the soft core into FPGA projects as a control unit by simplifying context switching and interrupt handling through dedicated shadow status registers. The architecture targets embedded systems with a single privilege level (machine mode), in which all threads operate within a unified administrative space, while protection and synchronization of shared data are handled at the software level. Following the RISC-V concept facilitates software development in high-level languages, although for small or highly specialized applications the use of virtual machines or domain-specific languages may be preferable. The implementation is reviewed for the minimal instruction set I+Zicsr, supporting integer operations and control and status registers, which are used to configure and control execution flow parameters for FPGA-based multithreaded control applications.