The proposed work focuses on design and implemention 1-bit magnitude comparator circuits using Quantum-dot Cellular Automata (QCA), a relatively new approach within nanotechnology for high-speed and energy-efficient computation. Two new designs for 1-bit magnitude comparators were developed with a focus on improving their performance in terms of cell count, area, and power dissipation. The first proposed design cut the number of QCA cells by 33%, the area by 11.2%, and the power dissipation by 10.5% compared to an existing benchmark design. The second proposed design was even more efficient, reducing the area by 43.8% and power dissipation by 24.5%, while maintaining all the intended functionality. These results show that QCA could be used to make compact, energy-efficient digital circuits. They also show that these kinds of designs could be used in multi-bit systems and other nanotechnology electronic applications.