Recently, the development of electronic design automation (EDA) tools for analog and millimeter-wave (mmWave) integrated circuits (ICs) design has become an increasing topic of research Pan et al in IEEE radio frequency integrated circuits symposium, 2018; Liu et al in IEEE Trans Comput Aided Des Integr Circ Syst 31(7):981–993, 2012; Passos et al in IEEE Trans Comput Aided Des Integr Circ Syst 39(12):4375–4384, 2020; Yin et al in IEEE Trans Comput Aided Des Integr Circ Syst 43(3), 705–715; Mendes et al in IEEE Trans Microw Theory Tech 73(8):4828–4841, 2025). In its foundation, these EDA tools use optimization algorithms that interact with circuit simulators and automatically explore the design space, i.e., simulation-based synthesis. Their objective is two-fold: unveil the design tradeoffs between the different performance targets, while pushing the performance boundaries of mmWave ICs to the capabilities of available deep nanometer technologies. However, to ensure that robust and industry-grade designs are attained, highly computationally expensive process, voltage and temperature (PVT) corner simulations must be mandatorily incorporated into their automatic synthesis (Mendes et al in IEEE Trans Microw Theory Tech 73(8):4828–4841, 2025. Still, simulating each sizing solution in a large set of testbenches is pushing modern workstations’ capabilities to their limits and incurring in prohibitive optimization times, taking days to weeks to complete (e.g., the PVT corner optimization conducted in (Vaz et al in IEEE international symposium on circuits and systems (ISCAS), 2022) took more than 25 days for a single voltage controlled oscillator (VCO) with 16 corner conditions). Therefore, to address these challenges, this Chapter presents a novel automatic sizing optimization framework for analog and mmWave ICs that bypasses the simulator using a set of parallel and independent PVT performance regressors based on artificial neural networks (ANN). To mitigate the need of acquiring computationally expensive and time-consuming PVT datasets, a transfer learning (TL) strategy, a mainstream approach in modern deep learning (DL) applications (Weiss et al in J Big Data 3(1), 2016), is employed to transfer knowledge from typical (TT) to PVT corner ANN-based performance regressors, in order to accelerate their development without compromising model accuracy, thereby eliminating the need to acquire large amounts of data to construct accurate and generalizable PVT performance estimators. Results obtained using the proposed sizing framework on the automatic PVT corner optimization of three low-noise amplifier (LNA) topologies, designed on a 65 nm node on the challenging 28 GHz band, show that this strategy can be employed to significantly accelerate mmWave design, with speed-ups ranging from 2.06× to 3.64× compared with full simulation synthesis, whilst obtaining competitive sizing designs.