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As overviewed in Chap. 2 of this book, recent advances in machine learning (ML) and deep learning (DL) are offering new alternatives to the design automation of analog integrated circuits (ICs) (Mina et al in Electron MDPI 11(3):435, 2022; Martins and Lourenço in IEEE Access 11:35965–35983, 2023; Wang et al in Proceedings of the IEEE international symposium on radio-frequency integration technology, 2024; Maji et al in Proceedings of the 29th Asia and South Pacific design automation conference, 2024; Martins in Microelectron MDPI 1(1, 2), 2025). These are being used on several distinct fronts such as on modeling (Suissa et al in IEEE Trans Comput Aided Des Integr Circ Syst 29(5):839–844, 2010), mapping from devices’ sizes to circuits’ performances (Wolfe and Vemuri in IEEE Trans Comput Aided Des Integr Circ Syst 22(2):198–212, 2003; Alpaydin et al in IEEE Trans Evol Comput 7(3):240–252, 2003; Liu et al in Proceedings 2002 design automation conference, pp 437–442, 2002), mapping from specifications to the devices’ sizes (Azevedo et al in Expert Syst Appl 290:128414, 2025; Eid et al in AEU—Int J Electron Commun 195:155767), layout generation (Zhu et al in Proceedings of the IEEE/ACM international conference on computer-aided design, 2019; Gusmão et al in Expert Syst Appl 207:117954, 2022; Gusmão et al in Appl Soft Comput 115:108188, 2022; Gusmão et al in ACM/IEEE design automation conference, 2021) or even fault testing (Andraud et al in IEEE Trans Circ Syst I: Regul Pap 63(11):2022–2035, 2016). In this regard, reinforcement learning (RL) is a branch of ML that has been increasing its presence in this field and has proven to achieve competitive results (Andraud et al in IEEE Trans Circ Syst I: Regul Pap 63(11):2022–2035, 2016; Settaluri et al in IEEE Trans Comput Aided Des Integr Circ Syst 41(9):2794–2807, 2022; Bao et al in IEEE Trans Comput Aided Des Integr Circ Syst 43(12):4398–4411, 2024; Cao et al in IEEE Trans Comput Aided Des Integr Circ Syst 44(2):627–640, 2025). But even though RL is a promising approach, the range of circuits and conditions to which it has been applied falls short of what would be desirable. The majority of works still only focus on optimizing the circuits’ functional behavior at nominal conditions, and therefore, not accounting for the significant performance degradation of circuits in the presence of process, voltage and temperature (PVT) variations. All these PVT variations are unavoidable, thus, designing robust circuits against PVT variations is of the utmost importance for modern electronic systems. To this end, this Chapter presents a comparative study of five different approaches for integrating PVT conditions within state-of-the-art RL-driven sizing methodologies. All approaches are evaluated under the same conditions, to ensure a fair comparison, and within the same circuit topology, comparing agent steps, number of simulations, execution time, and final sizing functional behavior. Additionally, five different reward functions are explored to assess their influence on agent performance and sizing quality. Results reveal the trade-offs of each approach, and the most effective strategy is identified and discussed.

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PVT Corner Conditions Within Reinforcement Learning-Based Analog IC Sizing

  • 章节

  • 发表日期：

    2026年

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  • Pedro Alberto Oliveira Paiva,
  • José Pedro Ponte Mota da Costa,
  • Filipe Parrado de Azevedo,
  • Ricardo Miguel Ferreira Martins

摘要

As overviewed in Chap. 2 of this book, recent advances in machine learning (ML) and deep learning (DL) are offering new alternatives to the design automation of analog integrated circuits (ICs) (Mina et al in Electron MDPI 11(3):435, 2022; Martins and Lourenço in IEEE Access 11:35965–35983, 2023; Wang et al in Proceedings of the IEEE international symposium on radio-frequency integration technology, 2024; Maji et al in Proceedings of the 29th Asia and South Pacific design automation conference, 2024; Martins in Microelectron MDPI 1(1, 2), 2025). These are being used on several distinct fronts such as on modeling (Suissa et al in IEEE Trans Comput Aided Des Integr Circ Syst 29(5):839–844, 2010), mapping from devices’ sizes to circuits’ performances (Wolfe and Vemuri in IEEE Trans Comput Aided Des Integr Circ Syst 22(2):198–212, 2003; Alpaydin et al in IEEE Trans Evol Comput 7(3):240–252, 2003; Liu et al in Proceedings 2002 design automation conference, pp 437–442, 2002), mapping from specifications to the devices’ sizes (Azevedo et al in Expert Syst Appl 290:128414, 2025; Eid et al in AEU—Int J Electron Commun 195:155767), layout generation (Zhu et al in Proceedings of the IEEE/ACM international conference on computer-aided design, 2019; Gusmão et al in Expert Syst Appl 207:117954, 2022; Gusmão et al in Appl Soft Comput 115:108188, 2022; Gusmão et al in ACM/IEEE design automation conference, 2021) or even fault testing (Andraud et al in IEEE Trans Circ Syst I: Regul Pap 63(11):2022–2035, 2016). In this regard, reinforcement learning (RL) is a branch of ML that has been increasing its presence in this field and has proven to achieve competitive results (Andraud et al in IEEE Trans Circ Syst I: Regul Pap 63(11):2022–2035, 2016; Settaluri et al in IEEE Trans Comput Aided Des Integr Circ Syst 41(9):2794–2807, 2022; Bao et al in IEEE Trans Comput Aided Des Integr Circ Syst 43(12):4398–4411, 2024; Cao et al in IEEE Trans Comput Aided Des Integr Circ Syst 44(2):627–640, 2025). But even though RL is a promising approach, the range of circuits and conditions to which it has been applied falls short of what would be desirable. The majority of works still only focus on optimizing the circuits’ functional behavior at nominal conditions, and therefore, not accounting for the significant performance degradation of circuits in the presence of process, voltage and temperature (PVT) variations. All these PVT variations are unavoidable, thus, designing robust circuits against PVT variations is of the utmost importance for modern electronic systems. To this end, this Chapter presents a comparative study of five different approaches for integrating PVT conditions within state-of-the-art RL-driven sizing methodologies. All approaches are evaluated under the same conditions, to ensure a fair comparison, and within the same circuit topology, comparing agent steps, number of simulations, execution time, and final sizing functional behavior. Additionally, five different reward functions are explored to assess their influence on agent performance and sizing quality. Results reveal the trade-offs of each approach, and the most effective strategy is identified and discussed.