As CMOS technology confronts persistent challenges in scaling, power consumption, and design complexity, achieving further miniaturization and performance gains has become increasingly difficult. CNTFETs are considered a viable alternative technology capable of overcoming CMOS limitations while maintaining both performance and reliability. An enhanced one-bit full adder using CNTFET implementation at 32 nm technology node, incorporating an optimized XOR-Majority gate structure. One-bit full adders based on CNTFETs demonstrate much better power efficiency, lower latency, and a reduced total power delay product. While prior works have shown power consumption reductions up to 73%, delay decreases of 29%, and PDP reductions of 81%, proposed work through its unique architectural enhancements, achieves an even greater power reduction 75% (1.75 μW), a significant delay improvement of 76% (7.1 ps), and an unprecedented 87% (32.66 × 10−18 Ws) overall PDP gain when operating over a supply power of 0.8 V to 1.2 V. Crucially, this robust performance is maintained with exceptional thermal stability, holding up consistently even under fluctuating temperatures (−25 °C to 75 °C), a critical aspect often less emphasized in previous works. To demonstrate its practical application, we constructed a 4-bit ripple carry adder using this 1-bit adder. Simulations confirm that this larger circuit also outperforms conventional designs, delivering faster, more power-efficient operation.

错误:搜索内容不能为空,请输入英文关键词
错误:关键词超出字数限制,请精简
高级检索

Performance Improvement of Full Swing Adder Using CNTFET

  • P. Durga Chandini,
  • K. Rajasekhar

摘要

As CMOS technology confronts persistent challenges in scaling, power consumption, and design complexity, achieving further miniaturization and performance gains has become increasingly difficult. CNTFETs are considered a viable alternative technology capable of overcoming CMOS limitations while maintaining both performance and reliability. An enhanced one-bit full adder using CNTFET implementation at 32 nm technology node, incorporating an optimized XOR-Majority gate structure. One-bit full adders based on CNTFETs demonstrate much better power efficiency, lower latency, and a reduced total power delay product. While prior works have shown power consumption reductions up to 73%, delay decreases of 29%, and PDP reductions of 81%, proposed work through its unique architectural enhancements, achieves an even greater power reduction 75% (1.75 μW), a significant delay improvement of 76% (7.1 ps), and an unprecedented 87% (32.66 × 10−18 Ws) overall PDP gain when operating over a supply power of 0.8 V to 1.2 V. Crucially, this robust performance is maintained with exceptional thermal stability, holding up consistently even under fluctuating temperatures (−25 °C to 75 °C), a critical aspect often less emphasized in previous works. To demonstrate its practical application, we constructed a 4-bit ripple carry adder using this 1-bit adder. Simulations confirm that this larger circuit also outperforms conventional designs, delivering faster, more power-efficient operation.