This paper presents the design and analysis of a web-based CPU microarchitecture simulator that enables manual configuration of key architectural parameters. The simulator provides an interactive environment for exploring the trade-offs between performance, power consumption, and energy efficiency across different CPU configurations. It supports both homogeneous and heterogeneous (big.LITTLE) systems, allowing users to adjust parameters such as core count, clock frequency, supply voltage, cache hierarchy, and workload intensity represented by the activity factor α. The environment integrates simplified models of CPU, memory, I/O subsystems, and thermal behavior, providing a holistic view of system-level performance. To demonstrate its capabilities, we conducted experiments with several configurations, ranging from energy-efficient “little” cores to overclocked high-performance “big” cores. Results highlight the fundamental trade-off between performance and efficiency: aggressive scaling of frequency and core complexity improves throughput but drastically reduces performance-per-watt and increases thermal load. The analysis also demonstrates the advantages of heterogeneous architectures, where big and LITTLE cores can be combined to achieve a more balanced performance–energy profile. The developed simulator offers practical value as both an educational tool for students studying computer architecture and a preliminary design instrument for engineers. It enables rapid experimentation, visualization of trends, and validation of architectural concepts without requiring complex simulation frameworks. Future work will focus on expanding the model library, improving accuracy with advanced thermal modeling, and integrating machine learning techniques for automated configuration optimization.