Data corruption happens when single or many cell interrupted fromexternal factors such as cosmic radiation, alpha and neutron particles, and the maximum temperature for space induce bit mistakes in on-chip memory in a die. For the sake of technical scaling, this occurs. Error detection and correction techniques (ECC) are used to repair defective data transmitted across a communication channel. In order to address radiation-induced MCUs in space-related memory applications, this study suggests a cutting-edge 2-dimensional error-correcting code that uses the divide-symbol. The diagonal bits, parity bits, and check bits were examined using the XOR technique in order to encode data bits. To obtain the data, a modified XOR operation was performed once more on the original encoded bits and the regenerated encoded bits. Verification, selection, and correction come after analysis. The suggested technique was simulated and synthesised using Xilinx ISE, which is integrated into verilog HDL. Compared to more popular contemporary methods, this encoding-decoding process has very low latency, very low power consumption, and very little space requirements.

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An Optimized Error Detection and Correction Codes for Space Engineering

  • Vennapusapalli Shavali,
  • Sancarapu Nagaraju,
  • Poola Subbarayudu,
  • Shaik Mahammadirshad,
  • Santhi Vandana Thudimella,
  • Syed Suraya

摘要

Data corruption happens when single or many cell interrupted fromexternal factors such as cosmic radiation, alpha and neutron particles, and the maximum temperature for space induce bit mistakes in on-chip memory in a die. For the sake of technical scaling, this occurs. Error detection and correction techniques (ECC) are used to repair defective data transmitted across a communication channel. In order to address radiation-induced MCUs in space-related memory applications, this study suggests a cutting-edge 2-dimensional error-correcting code that uses the divide-symbol. The diagonal bits, parity bits, and check bits were examined using the XOR technique in order to encode data bits. To obtain the data, a modified XOR operation was performed once more on the original encoded bits and the regenerated encoded bits. Verification, selection, and correction come after analysis. The suggested technique was simulated and synthesised using Xilinx ISE, which is integrated into verilog HDL. Compared to more popular contemporary methods, this encoding-decoding process has very low latency, very low power consumption, and very little space requirements.