We give a detailed comparison of a Strassen algorithm of \(4 \times 4\) matrix multiplication using ASIC based design approach. The implementation is based on open-source OpenLane 2 flow in combination with SkyWater 130 nm PDK. Five different levels of fixed-point precision 4, 6, 8, 10, 12 bits, are measured to comprehend the behaviour of physical design in relation to numerical accuracy. The divide and conquer approach by Strassen decreases the computational complexity of \(O(n^3)\) into \(O(n^{2.81})\) which is a definite benefit in terms of ASIC design where multipliers make up much of the silicon area and power cost. The findings demonstrate that the overall power rises nearly quadratically with bit precision, which rises between 33.31mW with 4 bit precision to 283.5 mW with 12 bit precision. There is a super-linear trend also inside the core area that is increasing to 97,988 to 405,209 \(\mu \textrm{m}^2\) . The analysis of timing also reveals that those designs with higher preciseness have a tough time with a 10ns timing requirement, the critical-path delay widening with precision: It is 8.725 ns at 10ns and 25.981 ns at 122.5 ns. The results are in line with the findings of prior studies that have emphasized the high power, area and delay cost of high-precision arithmetic in ASIC accelerators.