Deploying Transformer models on resource-constrained platforms like FPGAs requires balancing high computational throughput with limited hardware resources. This work is the first FPGA-based acceleration of the Fused-Weight Self-Attention (FWSA) mechanism, targeting ZCU104 board using Vitis HLS. To address the variability of Transformer dimensions and prevent resource saturation, we propose here an adaptive framework with three matrix multiplication approaches: Full Parallel for small matrices, Scalable for medium matrices, and Blocked for large matrices. Our design integrates a hybrid quantization scheme (INT8 weights, FP32 activations) to optimize resource usage while maintaining accuracy. Experimental results demonstrate that our FPGA implementation achieved up to 737×, 37×, and 7× lower latency compared to STM32L4, STM32H7, and GAP9 MCU baselines, respectively. While energy consumption increases, our findings establish a new SoA for accelerating critical Transformer blocks on mid-range FPGAs, paving the way for a feasible edge deployment for Large Language Models (LLM) within resources constraint.