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Quantized neural network kernels using very-low-precision arithmetic such as 4-bit integer weights are gaining popularity for their reduced memory requirements and enhanced computational efficiency. However, standard processor architectures are often not optimized for such fine-grained computations. In this paper, we investigate the utilization of the SIMD Within A Register (SWAR) technique to efficiently execute quantized DNN kernels with 4-bit integer weights. Leveraging bit-level parallelism through SWAR, we achieve significant speedups (up to 7 \(\times \) ) compared to standard implementations. We discuss the key SWAR-based implementation strategies and demonstrate their efficacy through experimental results. C++ source code available at https://github.com/lorenzograssi01/swaruint4 .

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Speeding up Quantized DNN Kernels Having 4-Bit Integer Weights Using the SWAR Approach

  • 会议论文

  • 发表日期：

    2026年

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  • Lorenzo Grassi,
  • Marco Cococcioni

摘要

Quantized neural network kernels using very-low-precision arithmetic such as 4-bit integer weights are gaining popularity for their reduced memory requirements and enhanced computational efficiency. However, standard processor architectures are often not optimized for such fine-grained computations. In this paper, we investigate the utilization of the SIMD Within A Register (SWAR) technique to efficiently execute quantized DNN kernels with 4-bit integer weights. Leveraging bit-level parallelism through SWAR, we achieve significant speedups (up to 7 \(\times \) ) compared to standard implementations. We discuss the key SWAR-based implementation strategies and demonstrate their efficacy through experimental results. C++ source code available at https://github.com/lorenzograssi01/swaruint4 .