Silicon Physically Unclonable Functions (PUFs) exploit intrinsic manufacturing variations to generate unique device-specific responses and serve as hardware roots of trust. Despite their promise, PUFs remain vulnerable to modeling attacks. Recent works propose using PAC learnability bounds as a formal measure to assess the modeling robustness of delay-based PUFs. In this work, we assess Priority Arbiter PUF (PA-PUF), a variant of the classical Arbiter PUF that incorporates a three-path chain and a priority-based arbitration mechanism. We provide the first provable learnability results for PA-PUF under the Deterministic Finite Automata (DFA) class. We extend the analysis to Feed-forward PA-PUF. We empirically validate the PAC learnability bounds using an implementation of Angluin’s L* algorithm, which achieves a modeling accuracy of 80% for a 32-bit PA-PUF with 8000 queries. Based on the formal analysis, we propose a generalization of the PA-PUF construction and analyze how the learnability outcomes change with varying design parameters. Finally, we evaluate the proposed generalized construction using state-of-the-art multi-layer perceptron (MLP)-based modeling attacks. Extensive experiments reveal that approximately \(2^{20}\) challenge-response pairs (CRPs) are sufficient to model a 64-bit PA-PUF with feed-forward with nearly 100% accuracy, while increasing the configuration to a generalized 12-path architecture reduces this accuracy to approximately 65%.