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The A novel approach to design and simulation of a Quadruple channel Fin-FET has been discussed in this research work. Effect of the Fin-width in the parameters like threshold voltage, DIBL, drain current at different gate voltage have been optimized. For 5 nm Fin-Width The designed structure shows the threshold voltage as 0.31 V, 22 mV/V DIBL, higher drain current and improved parameter than the conventional Fin-FET Structure. A 0.247 V threshold voltage has been optimized for 20 nm Fin Width.

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Design and Simulation of a Quadruple Channel Fin-FET Using T-CAD

  • 会议论文

  • 发表日期：

    2026年

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  • Ashok Kumar,
  • Roopesh Singh,
  • Shivam Verma

摘要

The A novel approach to design and simulation of a Quadruple channel Fin-FET has been discussed in this research work. Effect of the Fin-width in the parameters like threshold voltage, DIBL, drain current at different gate voltage have been optimized. For 5 nm Fin-Width The designed structure shows the threshold voltage as 0.31 V, 22 mV/V DIBL, higher drain current and improved parameter than the conventional Fin-FET Structure. A 0.247 V threshold voltage has been optimized for 20 nm Fin Width.