Verification of digital designs using traditional Verilog methodologies is often constrained by limited configurability, scalability and reusability, making them less effective for complex verification tasks. To address these challenges, this work presents a scalable and configurable Verification IP (VIP) for the Universal Asynchronous Receiver/Transmitter (UART) protocol, developed using SystemVerilog within the Universal Verification Methodology (UVM) framework. The novelty of the proposed VIP lies in its modular dual-agent architecture and runtime configurability-supporting features such as parity, word length, stop bits, duplex modes, error injection, and active/passive agent selection-thereby enabling the verification of any UART device with all the features of an operational UART interface. A functional coverage model has been designed to determine if the verification process covers all feasible cases or not. Coverage class reports coverage metrics, which are then analyzed to evaluate the effectiveness of the verification process. Both directed and random testcases are employed to achieve full coverage, with all simulations executed on Synopsys VCS.