This paper presents a comprehensive comparison of algorithmic-level design approaches for implementing unified multiplier hardware tailored for Falcon—an emerging post-quantum digital signature standard. A key requirement for Falcon is a 64-bit multiplier with a throughput of one multiplication per cycle that supports floating-point operations. While several multiplication techniques exist, their suitability depends on bit size, target technology, throughput, energy, and latency requirements. Our key novelty lies in conducting, for the first time, a systematic analysis and comparison of these techniques specifically for Falcon’s multiplier needs across both FPGA (Virtex-7 Series Xilinx) and ASIC (SkyWater 130nm node) platforms. We evaluate four approaches: a baseline design without optimizations, an asymmetric Tiling approach optimized for FPGA multiplier block utilization, Comba, and the Karatsuba algorithm. Surprisingly, on FPGAs, Karatsuba achieves the highest area efficiency (19.2% smaller than the baseline) despite pipelining and more operations, while Tiling outperforms in energy efficiency (35.9% improvement). For ASICs, Karatsuba remains the most area-efficient, but Comba exhibits unexpected energy efficiency advantages (51.5% better than Karatsuba and 22.8% better than baseline). These findings represent the first direct comparison of these techniques under these conditions, providing designers with actionable insights for optimizing Falcon hardware for specific applications and technologies.